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1 digital dc/dc pmbus 6a power module ZL9006M the ZL9006M is a 6a variable output, step-down pmbus-compliant digital power supply. included in the module is a high-performance digital pwm controller, power mosfets, an inductor, and all the passiv e components required for a highly integrated dc/dc power solution. this power module has built-in auto-compensation algorithms, which eliminates the need for manual compensation design work. the ZL9006M operates over a wide input voltage range and supports an output voltage range of 0.6v to 3.6v, which can be set by external resistors or via pmbus. only bulk input and output capacitors are needed to finish the design. the output voltage can be precisely regulated to as low as 0.6v with 1% output voltage regulation over line, lo ad, and temperature variations. the ZL9006M functions as a switch mode power supply with added benefits of auto comp ensation, programmable power management features, parametric monitoring, and status reporting capabilities. the ZL9006M is packaged in a thermally enhanced, compact (17.2mmx11.45mm) and low pr ofile (2.5mm) over-molded high-density array (hda) package module suitable for automated assembly by standard surface mount equipment. the ZL9006M is pb-free and rohs compliant. figure 1 represents a typical implementation of the ZL9006M. for pmbus operation, it is recommended to tie the enable pin (en) to sgnd. features ? complete digital switch mode power supply ? auto compensating pid filter ? 1% output voltage accuracy ? external synchronization ?output voltage tracking ? current sharing and phase interleaving ? programmable sequencing (delay and ramp time) ? snapshot? parametric capture ? pmbus compliant applications ?server, telecom, and datacom ? industrial and medical equipment ? general purpose point of load related literature ? see an2033 , ?zilker labs pmbus command set - ddc products? ? see an2034 , ?configuring current sharing on the zl2004 and zl2006? figure 1. typical application circuit figure 2. small footprint package with low profile at 2.5mm v in 2x22f 16v i 2 c/pmbus power-good output v out rtn 4.5v to c out enable ddc bus ext sync ZL9006M sync sa scl sda v1 fb+ fb- pg ddc sgnd en r sa r set dgnd 13.2v vdd vin (epad) vout (epad) pgnd (epad) 2.5mm 1 7 . 2 m m 1 1 . 4 5 m m *patent pending package march 5, 2013 fn7959.0 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc, 2013. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
ZL9006M 2 fn7959.0 march 5, 2013 table of contents pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 pinout internal circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 typical performance curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 derating curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 internal bias and input voltage considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 pre-programming configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 design trade-offs with switching frequenc y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 completing a power supply design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 selection of the input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 selection of the output capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 multi-mode pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 i 2 c/pmbus communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 i 2 c/pmbus module address selectio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 phase spreading for a single-phase mode of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 start-up procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 soft-start delay and ramp times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 power-good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 switching frequency and pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 adaptive diode emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 input undervoltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 output overvoltage protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 output pre-bias protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 output overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 thermal overload protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 voltage tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 tracking groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 voltage margining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 digital-dc bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 output sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 fault spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 monitoring via i 2 c/pmbus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 temperature monitoring using the xtemp pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 snapshot parameter capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 non-volatile memory and device security features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 layout guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 package description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 pcb layout pattern design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 thermal vias. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 stencil pattern design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 reflow parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 about intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
ZL9006M 3 fn7959.0 march 5, 2013 pin configuration ZL9006M (32 ld hda) top view v25 v25 pg en ddc xtemp vdd vdd 1 vin sw 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 a b c d e f g h j k l vout sgnd sgnd dgnd sync sa scl sda salrt fc0 v1 1 2 3 4 5 6 7 8 9 1011121314151617 v1 ss vtrk fb+ fb- isenb vr pgnd pad1 pad3 pad4 pad5 v25 v25 pad2 pgnd pin descriptions pin label type description a1, a2, b3, b6 v25 pwr internal 2.5v reference. it is used to power internal circuitry. a3 pg 0 power-good output . provide open-drain power-good signal. by defaul t, the pg pin asserts if the output is within +15/-10% of the target voltage. these limits and the polarity of the pin may be changed via the i 2 c/pmbus interface. a4 en i enable input. this pin is factory set as active high. pull-up to enable the module switching and pull-down to disable switching. if the module is controlled through pmbus command, tie a 10k ? resistor from this pin to sgnd to avoid this pin floating. a5 ddc i/o digital-dc bus (open drain). the ddc pin on all digital modules in one application should be connected together. this dedicated bus provides the communication channel between mo dules for features such as sequencing, fault spreading, and current sharing. a6 xtemp i external temperature sensor input. connect to an external 2n3904 transistor with a diode configuration (see figure 25 on page 24). a7, a8 vdd pwr controller input voltage. tie to vin directly. c1 sgnd pwr signal ground. connect to low impedance ground plane. d1 dgnd pwr digital ground. common return for digital signals. co nnect to low impedance ground plane. e1 sync i/o clock synchronization. used for synchronization to external frequency reference. f1 sa i serial address select pin. used to assign unique pmbus address to each module and phase spreading. f10 pgnd pwr power ground. connect to low impedance ground plane. g1 scl i/o serial clock . i 2 c/pmbus interface pin. h1 sda i/o serial data . i 2 c/pmbus interface pin. h9 vr pwr internal 5v reference. used to power internal drivers. the current limit for the vr pin is 10ma. please consider this when using the vr pin for driving external circuitry. j1 salrt o serial alert . i 2 c/pmbus interface pin. k1 fc0 i mode setting. used to set the single-phase/current sharing mo de, auto-compensation, and sync configuration (see table 9 on page 19).
ZL9006M 4 fn7959.0 march 5, 2013 l1, l2 v1 i output voltage selection pin. used to program the output voltage through pin-strap setting or connecting a resistor from the v1 pin to sgnd (see table 4 on page 15). the set voltage on this pin is the maximum allowed output voltage in i 2 c/pmbus programming. l3 ss i soft-start pin. set ss pin by pin-strapping or connecting a resistor to sgnd using the appropriate resistor. the pin can program the delay from when en is asserted until the output voltage starts to ramp, the output voltage ramp time during turn on/off, and input undervoltage lockout (uvlo) level (see table 6 on page 17). this pin can also set tracking ratio and upper track limit (see table 10 on page 21) . l4 vtrk i tracking sense input. used to track an external voltage source. l6 fb+ i output voltage positive feedback. positive inputs of differen tial remote sense for the regulator. connect to the output rail or the regulation point of load/processor. l7 fb- i output voltage negative feedback. negative input of the differential remote sense for the regulator. connect to the negative rail or ground of the load/processor. l8 isenb i test pin. for factory test use. solder down the pin for mechanical strength, but do not connect the pin. pad1 vin pwr power inputs. input voltage range: 4.5v to 13.2v. tie directly to the input rail. when the input is between 4.5v to 5.5v, vin should be tied directly to vcc. pad2 pgnd pwr power ground. power ground pins for both input and output returns. pad3 sgnd pwr signal ground. connect to low impedance ground plane (see figure 26 on page 25). pad4 sw pwr switch node. use for monitoring switching frequency. sw pad should be floating or used for snubber connections. to achieve better thermal performance, the sw planes can also be used for heat removal with thermal vias connected to large inner layers (see figure 26 on page 25). pad5 vout pwr power output. apply output load between these pins and pgnd pins. output voltage range: 0.6v to 3.6v. pin descriptions (continued) pin label type description
ZL9006M 5 fn7959.0 march 5, 2013 pinout internal circuit gl gh vcc gnd v1 vr vdd pwml scl ddc sa en pg v25 sync sgnd dgnd vtrk pwmh communication sda adc csa vsa supervisor temp sensor adc protection digital compensator oc/uc d-pwm pll sync out gate drive logic nlr power management ldo ldo ss mgn ov/uv current share interleave autocomp nvm vdd digital controller gate driver fb+ fb- vout vin pgnd sgnd l 3 sw 1.0h 22 22 filter l6 e1 g1 j1 f1 l7 14 14 14 a2 h9 a7 l1 l3 a4 pad 4 14 v25 b3 a8 vdd pad 5 vout h1 v1 l2 pad 1 pad 2 pad 3 v25 b6 v25 a1 d1 dgnd c1 sgnd xtemp a6 f10 pgnd salrt a5 fc0 k1 ss l4 a3 isenb l8 10f 2f ordering information part number (notes 1, 2, 3) part marking temp range (c) package (pb-free) pkg. dwg. # ZL9006Mirz ZL9006M -40 to +85 32 ld 17.2x11.45 hda y32.17.2x11.45 notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets; molding compounds/die attach materials and nipdau plate -e4 termination finish, which is rohs compliant and compatible with both snpb and pb-free sold ering operations. intersil pb-fre e products are msl classified at pb-free peak reflow temp eratures that meet or exceed the pb-fr ee requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device information page for ZL9006M . for more information on msl please see tech brief tb363 .
ZL9006M 6 fn7959.0 march 5, 2013 absolute maximum ratings (note 4) thermal information dc supply voltage for vdd pin . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 17v input voltage for vin pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 17v mosfet drive reference for vr pin . . . . . . . . . . . . . . . . . . . . -0.3v to 6.5v 2.5v logic reference for v25 pin. . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 3v logic i/o voltage for pg, en, ddc, sync, pg, scl, sda, salrt, fc0, v1, ss pins . . . . . . . . . . . . . . . . . -0.3v to 6v analog input voltages xtemp, vtrk, fb+, fb-, isenb pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6v switch node for sw pin continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(pgnd - 0.3v) to 30v transient (<100ns) . . . . . . . . . . . . . . . . . . . . . . . . . . . . (pgnd - 5v) to 30v ground voltage differential (dgnd - sgnd, pgnd - sgnd) for dgnd, sgnd and pgnd pins . . . . . . . . . . . . . . . . . . . . -0.3v to +0.3v esd rating human body model (tested per jesd22-a114f) . . . . . . . . . . . . . . 2000v machine model (tested per jesd22-a115c) . . . . . . . . . . . . . . . . . . 200v charged device model (tested per jesd22-c110d) . . . . . . . . . . . . 750v latch up (tested per jesd78c; class 2, level a) . . . . . . . . . . . . . . . 100ma thermal resistance (typical) ja (c/w) jc (c/w) 32 ld hda package (notes 7, 8) . . . . . . . . 17 1 storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions input supply voltage range, v in . . . . . . . . . . . . . . . . . . . . . . 4.5v to 13.2v input supply for controller, v dd (note 5). . . . . . . . . . . . . . . . . 4.5v to 13.2v driver supply voltage, vr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5v to 5.5v output voltage range, v out (note 6) . . . . . . . . . . . . . . . . . . . 0.54v to 3.6v output current range, i out(dc) (note 18) . . . . . . . . . . . . . . . . . . . 0a to 6a operating junction temperature range, t j . . . . . . . . . . . .-40c to +125c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. voltage measured with respect to sgnd. 5. v in supplies the power fets. v dd supplies the controller. v in can be tied to v dd . for v dd 5.5v, v dd should be tied to vr. 6. includes 10% margin limits. 7. ja is simulated in free air with device mounted on a four-layer fr-4 test board (76.2 x 114.3 x 1.6mm) with 80% coverage, 2oz cu on top and bottom layers, plus two, buried, one-ounce cu layers with coverage acro ss the entire test board area. multiple vias were used, with vi a diameter = 0.3mm on 1.2mm pitch. 8. for jc , the ?case? temperature is measured at the center of the package underside. electrical specifications v in = v dd = 12v, t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c. parameter conditions min (note 9) typ (note 10) max (note 9) unit input and supply characteristics input bias supply current, i dd v in = vdd = 13.2v, f sw = 400khz, no load ? 35 45 ma input bias shutdown current, i dds en = 0v, no i 2 c/pmbus activity ? 15.5 20 ma input supply current, i vin v in = 12v, i out = 6a, v out = 1.2v, f sw = 400khz ?0.74?a vr reference output voltage (note 11) v dd > 6v 4.5 5.2 5.7 v v25 reference output voltage (note 11) v r > 3v 2.25 2.5 2.75 v output characteristics output voltage adjustment range (note 11) v in > v out . does not include margin limits 0.6 ? 3.3 v output voltage set-point resolution set us ing resistors. (see table 1) ? 50 - 200 ? mv set using i 2 c/pmbus with temperature compensation applied ? 0.025 ? % fs output voltage accuracy (notes 11, 12) includes line, load, temperature -1 ? 1 % vsen input bias current (note 11) vsen = 5.5v ? 110 200 a output load current (note 19) v in = 12v, v out = 1.2v ? 6 ? a peak-to-peak output ripple voltage, v out (note 12) i out = 6a, v out = 1.2v, c out = 1000f ? 20 ? mv soft-start delay duration range (notes 11, 13) set using ss pin or resistor 5 ? 20 ms set using i 2 c/pmbus 0.005 ? 500 s
ZL9006M 7 fn7959.0 march 5, 2013 soft-start delay duration accuracy (notes 11, 13) turn-on delay (note 15) - -0.25/+4 - ms turn-off delay (note 15) - -0.25/+4 - ms soft-start ramp duration range (notes 11, 13) set using ss pin or resistor 2 ? 20 ms set using i 2 c 0 ? 200 ms soft-start ramp duration accuracy (note 11) ? 100 ? s dynamic characteristics voltage change for positive load step i out = 1.2a to 6a, slew rate = 1.6a/ s, v out = 1.2v (see figure 19) ?4?% voltage change for negative load step i out = 6a to 1.2a, slew rate = 1.6a/ s, v out = 1.2v (see figure 19) ?4?% oscillator and switching characteristics (note 11) switching frequency range 300 ? 1000 khz switching frequency set-point accuracy predefined settings (see table 1) -5 ? 5 % maximum pwm duty cycle factory setting (note 18) - ? 95 % minimum sync pulse width 150 ??ns input clock frequency drift tolerance external clock source -13 ? 13 % logic input/output characteristics (note 11) pmbus speed ?100?khz logic input bias current en, pg, scl, sda pins -10 ? 10 a logic input low, v il ?? 0.8 v logic input high, v ih 2.0 ??v logic output low, v ol i ol 4ma (note 17) ? ? 0.4 v logic output high, v oh i oh -2ma (note 17) 2.25 ??v tracking (note 11) vtrk input bias current vtrk = 5.5v ? 110 200 a vtrk tracking ramp accuracy 100% tracking, v out -vtrk, no prebias -100 ? + 100 mv vtrk regulation accuracy 100% tracking, v out -vtrk -1 ? 1 % fault protection characteristics (note 11) uvlo threshold range configurable via i 2 c/pmbus 2.85 ? 16 v uvlo set-point accuracy -150 ? 150 mv uvlo hysteresis factory setting ? 3 ? % configurable via i 2 c/pmbus 0 ? 100 % uvlo delay ?? 2.5 s power-good v out threshold factory setting ? 90 ? % v out power-good v out hysteresis factory setting ? 5 ? % power-good delay (note 16) configurable via i 2 c/pmbus 0 ? 500 s vsen undervoltage threshold factory setting ? 85 ? % v out configurable via i 2 c/pmbus 0 ? 110 % v out electrical specifications v in = v dd = 12v, t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter conditions min (note 9) typ (note 10) max (note 9) unit
ZL9006M 8 fn7959.0 march 5, 2013 vsen overvoltage threshold factory setting ? 115 ? % v out configurable via i 2 c/pmbus 0 ? 115 % v out vsen undervoltage hysteresis ?5?% v out vsen undervoltage/overvoltage fault response time factory setting ?16?s configurable via i 2 c/pmbus 5 ? 60 s thermal protection threshold (controller junction temperature) factory setting ? 125 ? c configurable via i 2 c/pmbus -40 ? 125 c thermal protection hysteresis ?15?c notes: 9. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 10. parameters with typ limits are not prod uction tested unless otherwise specified. 11. parameters are 100% tested for internal controller prior to module assembly. 12. v out measured at the termination of the fb+ and fb- sense points. 13. the device requires a delay period following an enable signal and prior to ramping its output. 14. precise ramp timing mode is only valid when using the en pin to enable the device rather than pmbus enable. 15. the devices may require up to a 4ms delay following the assert ion of the enable signal (normal mode) or following the de-ass ertion of the enable signal. 16. factory setting for power-good delay is set to the same value as the soft-start ramp time. 17. nominal capacitance of logic pins is 5pf. 18. maximum duty cycle is limited by the equation max_duty(%) = [1 - (15010 -9 f sw )] 100 and not to exceed 95%. 19. the load current is related to the thermal derating curves. the maximum allowed current is derated while the output voltage goes higher than 2.5v. electrical specifications v in = v dd = 12v, t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter conditions min (note 9) typ (note 10) max (note 9) unit
ZL9006M 9 fn7959.0 march 5, 2013 typical performance curves operating conditions: t a = +25c, no air flow, c out = 3 x 100f + 1 x 330f. typical values are used unle ss otherwise noted. figure 3. ZL9006M efficiency, v in = 5v figure 4. ZL9006M efficiency, v in = 12v figure 5. v out = 1.2v transient response figure 6. v out = 1.8v transient response figure 7. v out = 2.5v transient response figure 8. v out = 3.3v transient response 60 65 70 75 80 85 90 95 100 0 1 2 3 4 5 6 i out (a) 0.6v 400khz 1.0v 400khz 1.2v 400khz 1.8v 615khz 2.5v 615khz 3.3v 471khz efficency (%) 40 45 50 55 60 65 70 75 80 85 90 95 100 0 1 2 3 4 5 6 efficency (%) i out (a) 0.6v 400khz 1.0v 400khz 1.2v 400khz 1.8v 615khz 2.5v 800khz 3.3v 800khz v in = 12v v out = 1.2v i out step = 1.2a to 6a slew 1.6a/s f sw = 615khz 100mv/div 2a/div 200s/div v in = 12v v out = 1.8v i out step = 1.2a to 6a slew 1.6a/s f sw = 615khz 100mv/div 2a/div 200s/div v in = 12v v out = 2.5v i out step = 1.2a to 6a slew 1.6a/s f sw = 615khz 100mv/div 2a/div 200s/div v in = 12v v out = 3.3v i out step = 1.2a to 6a slew 1.6a/s f sw = 800khz 100mv/div 2a/div 200s/div
ZL9006M 10 fn7959.0 march 5, 2013 figure 9. v out = 1.2v output voltage ripple figure 10. v out = 1.8v output voltage ripple figure 11. v out = 2.5v output voltage ripple figure 12. v out = 3.3v output voltage ripple figure 13. soft-stop ramp-down figure 14. soft-start ramp-up typical performance curves operating conditions: t a = +25c, no air flow, c out = 3 x 100f + 1 x 330f. typical values are used unle ss otherwise noted. (continued) 20mv/div 20mv/div 2s/div 20mv/div v in = 12v v out = 1.2v f sw = 615khz 20mv/div 20mv/div 2s/div 20mv/div v in = 12v v out = 1.8v f sw = 615khz 20mv/div 20mv/div 2s/div 20mv/div v in = 12v v out = 2.5v f sw = 615khz 20mv/div 20mv/div 2s/div 20mv/div v in = 12v v out = 3.3v f sw = 800khz -0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 012345678910 time (ms) v out (v) v out = 1.2v t fall = 5ms v in = 12v -0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 012345678910 time (ms) v out (v) v out = 1.2v t rise = 5ms v in = 12v
ZL9006M 11 fn7959.0 march 5, 2013 derating curves operating conditions: t a = +25c, no air flow. f sw corresponds to those used in efficiency curves. c out = 3 x 100f + 1 x 330f. typical values are us ed unless otherwise noted. figure 15. derating curve, 5v in for various output voltages, no air flow figure 16. derating curve, 12v in for various output voltages, no air flow figure 17. power loss curve, 5v in for various output voltages figure 18. power loss curve, 12v in for various output voltages 0 1 2 3 4 5 6 60 70 80 90 100 110 120 ambient temperature (c) 5v in _1v out 5v in _3.3v out load current (a) 0 1 2 3 4 5 6 60 70 80 90 100 110 120 12v in _1v out 12v in _1.8v out 12v in _3.3v out ambient temperature (c) load current (a) 0.0 0.5 1.0 1.5 01 23 4 56 i out (a) 1.0v 400khz 3.3v 471khz loss (w) 0.0 0.5 1.0 1.5 2.0 2.5 0123456 loss (w) i out (a) 1.0v 400khz 1.8v 615khz 3.3v 800khz
ZL9006M 12 fn7959.0 march 5, 2013 application information internal bias and input voltage considerations beside vin supplying the main power conversion, the ZL9006M employs two internal low dropout (ldo) regulators to supply bias voltages for internal circuitry allo wing it to operate from a single input supply. the internal bias regulators are as indicated in the following: vr - the vr ldo provides a regulated 5v bias supply for the mosfet driver circuits. it is powered from the vdd pin. v25 - the v25 ldo provides a regulated 2.5v bias supply for the main controller circuitry. it is powered from an internal 5v node. when the input supply (vdd) is higher than 5.5v, the vr pin should not be connected to any other pin. due to the dropout voltage associated with the vr bias regula tor, the vdd pin can be connected to the vr pin for designs operating from a supply below 5.5v. the internal bias regulators are no t designed to be outputs for powering other circuitry, so keep current into the vdd pin below 80ma. typically, vdd is connected directly to vin. in the case that vdd is powered separately from vin, the recommended power sequence is to keep en low, power vdd, and then vin. when the voltage is applied to vin, vdd should also be applied to avoid unintentional turn-on of the intern al high-side mosfet. if the vdd voltage is different from vin, pre-bias start-up and auto-compensation may not work co rrectly as the vdd voltage is used to measure input voltage as part of the pre-bias and auto-compensation calculation. pre-programming configuration the intersil digital power module allows pre-programming before the main power rail is supplied to the vin pins of the module. if the system bias (i.e., 3.3v bias) is available, the power module can be programmed to load the co nfiguration file or change the settings without main power being on. see figure 20 for an example with 3.3v bias voltag e and 12v input voltage for the main power rail. to pre-program the module without applying power to the vin pin, the bias voltage 3.3v is applied to pin vr through a schottky diode such that 3.0 < vr and < vdd when vin is applied. the body diode of the pmos will be reverse biased, preventing back feeding to the vin rail. when the main power rail 12v vin is on, the pmos is on to supply the power to the module. in this case, only a small voltage is dropped on the pmos, so the controller can st ill detect the input voltage accurately. if there are more intersil digital modules on the board, only one pmos (as shown in figure 20) is required to drive the vin voltages of all modules. figure 19. test circuit for all performance and derating curves notes: 20. the i 2 c/pmbus requires pull-up resistors. please refer to the i 2 c/pmbus specifications for more details. 21. the ddc bus requires a pull-up resistor. the resistance will va ry based on the capacitive loading of the bus (and on the num ber of devices connected). the 10k ? default value, assuming a maximum of 100pf per device, provides the necessary 1s pull-up rise time. please refer to ?digital- dc bus? on page 23 for more details. 22. additional capacitance may be required to meet specific transient response targets. salrt sda scl ddc en c5 100f ferrite bead blm15bd102sn1d, or 2.2 ? c2 22f c3 330f (optional) ZL9006M vdd.a8 a8 vdd.a7 a7 xtemp a6 ddc a5 en a4 pg a3 v25.a2 a2 sgnd.c1 c1 dgnd d1 v25.a1 a1 sa f1 vin pad1 sw pad4 vout pad5 sync e1 scl g1 sgnd.pad3 pad3 pgnd.pad2 pad2 sda h1 salrt j1 fc0 k1 v1.l1 l1 v1.l2 l2 ss l3 vtrk l4 fb+ l6 fb- l7 isenb l8 vr h9 pgnd.f10 f10 v25.b3 b3 v25.b6 b6 c1 22f rset c7 330f c6 100f rsa c4 100f sgnd sgnd vin sgnd sgnd gnd vout gnd (note 20 ) ( n o t e 2 1 ) i 2 c/pmbus (see table 3 for rsa value) (see table 4 for rset value) (note 22 )
ZL9006M 13 fn7959.0 march 5, 2013 design trade-offs with switching frequency for design of the buck power st age, there is a trade-off when choosing switching frequency to achieve higher power supply efficiency, output ripple, and transient response. for output voltages below 2.0v, a lower switch ing frequency results in higher efficiency. a lower output ripple and faster transient response is achieved with higher switching frequencies, and thereby can reduce the required amount of output capacitance. also, given an input to output voltage relation, there is a limitation on the allowable switching frequency due to normal part operation. see ?switching frequency and pll? on page 18 for more considerations. to start the design with a goal of high efficiency, select a frequency based on table 1. to achieve good transient response, a minimum switching frequency of 615khz is recommended. completing a power supply design to achieve a power supply design with digital capabilities using the ZL9006M, only input and output capacitors and two resistors are needed. the two resistors are in stalled on the sa and v1 pins for setting the i 2 c address and output voltage, respectively. selection of the input capacitor the input filter capacitor should be based on how much ripple the supply can tolerate on the dc input line. the larger the capacitor, the less ripple expected, but consideration should be taken for the higher surge current during power-up. the ZL9006M provides the soft-start fu nction that controls and limits the current surge. the value of the input capacitor can be calculated by equation 1: where: c in(min) is the minimum input capacitance (f) required i o is the output current (a) d is the duty cycle (v o /v in ) v p-p(max) is the maximum peak-to-peak voltage (v) f s is the switching frequency (hz) in addition to the bulk capacita nce, some low equivalent series resistance (esr) ceramic capacitance should be placed as close as possible to decouple between the drain terminal of the high side mosfet (vin pad1) and the so urce terminal of the low side mosfet (pgnd pad2). this is used to reduce voltage ringing created by the switching current across parasitic circuit elements. this ripple?s (i cinrms ) impact should be considered, and can be determined from equation 2: without capacitive filtering near the power supply circuit, this current would flow through the supply bus and return planes, coupling noise into other system circuitry. the input capacitors should be rated at 1.2x the ripple current calculated in equation 2 to avoid overheating of the capacitors due to the high ripple current, which can cause premature failure. selection of the output capacitors the ZL9006M is designed for low output voltage ripple. the output voltage ripple an d transient requirements can be met with bulk output capacitors (c out) with low esr; the recommended minimum esr is <6m ? . c out can be a low esr tantalum capacitor, a low esr polymer capacitor or a ceramic capacitor. the typical output capacitance range is from 200f to 1200f, and decoupling ceramic output capacitors are used per phase. the optimized ou tput capacitance is 700f with an esr of 5m ? . the maximum recommended produc t of output capacitance and equivalent esr value is given by [c out x esr] < 3600 (f x m ? ) . with a step load faster than 0.2a/s, the recommended amount of output capacitor is 100f per ampere of step load. additional output filtering may be needed if further reduction of output ripple or dynamic transient spikes are required. functional description multi-mode pins in order to simplify circui t design, the ZL9006M family incorporates patented multi-mode pins that allow the user to easily configure many aspects of the device without programming. most power ma nagement features can be configured using these pins. the multi-mode pins can respond to two types of configurations summar ized in table 2: pin strapping and resistor programming. these pins are sampled when power is applied or by issuing a pmbus re store command (see application note an2033 ). with pin strapping, parameters ca n be set by strapping the pins in one of three possible states: low, open, or high. these pins can be connected to sgnd for logic low as this pin provides a voltage lower than 0.8v. for logic open, they have no connection. these pins can be connected to the v25 pin for logic high settings as this pin provides a re gulated voltage higher than 2v when power is applied to the vdd pin. resistor programming allows a greater range of adjustability when connecting a finite value re sistor (in a specified range) between the multi-mode pin and sgnd. standard 1% resistor values are used, and only every fo urth standard resistor value is used so the device can reliably recognize the value of resistance figure 20. pre-programming configuration table 1. optimal switching frequency for efficiency v 0 -vin 3.3v (khz) 5.0v (khz) 12.0v (khz) 0.6 - 1.5 300 400 400 1.5 - 2.5 300 615 615 2.5 - 3.6 300 471 800 c in min () i o d1d ? () ? v p-p max () f s ? ------------------------------------------- ? = (eq. 1) (eq. 2) i cinrms i out d1d ? () =
ZL9006M 14 fn7959.0 march 5, 2013 connected to the pin while eliminating the error associated with the resistor accuracy. up to 31 unique selections are available using a single resistor. there are five multi-mode pins in ZL9006M: fc0, sa, sync, ss, v1. the multi-mode pin config uration can set ZL9006M power management features and mode of operation to both single-phase and current-sharing without any programming. sa and v1 are the only two pins that must be set for a general single-phase operation, which use the default settings associated with the other three pins, or overriding other parameters via the i 2 c/pmbus. sa sets the i 2 c address, phase spreading, and reference/member assignment in current sharing mode. the effective phase spreading depends on the mode of operation. the reference/member is pre-assigned in current sharing mode, and up to 8 two-phase with 5 three-phase current-shared group is possible. fc0 is used to distinguish between the two modes of operation, and is used in combination with sa in current sharing mode. fc0 pin strapping and resistor pr ogramming in the range of 10k ? -42.2k ? set the operation to single-phase mode, while the range of 46.4k ? -178k ? is for current sharing mode. fc0 also sets the autcomp and sync configuration. sync sets the switching frequenc y, and is only effective in single-phase mode, as sync pi ns are connected together in current-sharing mode. ss sets the ramp timing, uvlo, an d tracking. v1 sets the output voltage. ss and v1 are the same purpose in single-phase and current-share modes. i 2 c/pmbus communications the ZL9006M provides an i 2 c/pmbus digital interface that enables the user to configure all aspects of the module operation as well as monitor the input and output parameters. the ZL9006M can be used with any i 2 c host device. in addition, the module is compatible with pmbu s version 2.0 and includes an salrt line to help mitigate ba ndwidth limitations related to continuous fault monito ring. pull-up resistors are required on the i 2 c/pmbus as specified in the pmbus 2.0 specification. the ZL9006M accepts most standard pmbus commands. when controlling the device with pmbus commands, it is recommended that the enable pin be tied to sgnd. the pmbus device address and vout_max are the only parameters that must be set by external pins. all other device parameters can be set via the i 2 c/pmbus. the device address is set using the sa pin. vout_max is determined as 10% greater than the voltage set by the v1 pin. ZL9006M supports 100khz and 400khz i 2 c clock speed with communication interval of 20ms between store and restore commands, and ~2ms for other general commands. i 2 c/pmbus module address selection each module must have its own unique serial address to distinguish between other devices on the bus. the module address is set by connecting a resistor between the sa pin and sgnd. table 3 lists the available module addresses. table 2. multi-mode pin configuration pin tied to value low (logic low) <0.8v dc open (n/c) no connection high (logic high) >2.0v dc resistor to sgnd set by resistor value table 3. pmbus address values r sa (k ? )pmbus address low 0x23 open 0x24 high 0x25 10 0x50 11 0x51 12.1 0x52 13.3 0x53 14.7 0x54 16.2 0x55 17.8 0x56 19.6 0x57 21.5 0x58 23.7 0x59 26.1 0x5a 28.7 0x5b 31.6 0x5c 34.8 0x5d 38.3 0x5e 42.2 0x5f 46.4 0x60 51.1 0x61 56.2 0x62 61.9 0x63 68.1 0x64 75 0x65 82.5 0x66 90.9 0x67 100 0x68 110 0x69 121 0x6a 133 0x6b 147 0x6c 162 0x6d 178 0x6e
ZL9006M 15 fn7959.0 march 5, 2013 phase spreading for a single-phase mode of operation when multiple point-of-load converters share a common dc input supply, it is desirable to adjust the clock phase offset of each device such that not all devices start to switch simultaneously. setting each converter to start its switching cycle at a different point in time can dramatically reduce input capacitance requirements and efficiency losses. since the peak current drawn from the input supply is effectively spread out over a period of time, the peak current drawn at any given moment is reduced, and the power losses proportional to the i rms 2 are reduced dramatically. to enable spreading, all converters must be synchronized to the same switching clock. the fc0 pin is used to set the configuration of the sync pin fo r each device as described in ?switching frequency and pll? on page 18. selecting the phase offset for the device in a standalone mode of operation is accomplished by selecting a device address according to the following equation: phase offset = device address x 45 for example: ? a device address of 0x50 or 0x60 would configure no phase offset ? a device address of 0x51 or 0x61 would configure 45 of phase offset ? a device address of 0x52 or 0x62 would configure 90 of phase offset the phase offset of each device may also be set to any value between 0 and 360 in 22.5 increments via the i 2 c/pmbus interface. refer to application note an2033 for further details. output voltage selection the output voltage may be set to a voltage between 0.6v and 3.6v provided that the input volt age is higher than the desired output voltage by an amount su fficient to prevent the device from exceeding its maximum duty cycle specification. the v1 pins are used to set the output voltage using a single resistor, r set between the v1 pins and sgnd. table 4 lists the available output voltage settings with a single resistor. the output voltage may also be set to any value between 0.6v and 3.6v using a pmbus command over the i 2 c/pmbus interface. see application note an2033 for details. the r set resistors program places an upper limit in output voltage setting through pmbus programming to 10% above the value set by the resistors. table 4. single resistor v out setting r set (k ? )v out low 1.20 open 1.50 high 3.30 10 0.60 11 0.65 12.1 0.70 13.3 0.75 14.7 0.80 16.2 0.85 17.8 0.90 19.6 0.95 21.5 1.00 23.7 1.05 26.1 1.10 28.7 1.15 31.6 1.20 34.8 1.25 38.3 1.30 42.2 1.40 46.4 1.50 51.1 1.60 56.2 1.70 61.9 1.80 68.1 1.90 75 2.00 82.5 2.10 90.9 2.20 100 2.30 110 2.50 121 2.80 133 3.00 147 3.30 162 3.60 table 4. single resistor v out setting (continued) r set (k ? )v out
ZL9006M 16 fn7959.0 march 5, 2013 start-up procedure the ZL9006M follows a specific internal start-up procedure after power is applied to the vdd pin. table 5 describes the start-up sequence. if the device is to be synchronized to an external clock source, the clock frequency must be stable pr ior to asserting the en pin. the device requires approximately 5ms to 6ms to check for specific values stored in its internal memory. if the user has stored values in memory, those values will be loaded. the device will then check the status of all multi-mo de pins and load the values associated with the pin settings. once this process is completed, the device is ready to accept commands via the i 2 c/pmbus interface and the device is ready to be enabled. once enabled, the device requires a minimum delay period following an enable signal and prior to ramping its output, as described in ?soft-start delay and ramp times? on page 17. if a soft-start delay pe riod less than the minimum has been configured (using pmbu s commands), the device will default to the minimum delay period. if a delay period greater than the minimum is configured, the device will wait for the configured delay period prior to starting to ramp its output. after the delay period has expired, the output will begin to ramp towards its target voltage according to the pre-configured soft-start ramp time that has been set using the ss pin. it should be noted that if the en pin is ti ed to vdd, the device will still require approximately 5ms to 6m s before the output can begin its ramp-up as described in table 5. table 5. ZL9006M start-up sequence step # step name description time duration 1 power applied input voltage is applied to the ZL9006M?s vdd pin depends on input supply ramp time 2 internal memory check the device will check for va lues stored in its internal memory. this step is also performed after a restore command. approximately 5ms to 6ms (device will ignore an enable signal or pmbus traffic during this period) 3 multi-mode pin check the device loads valu es configured by the multi-mode pins. 4 device ready the device is ready to accept an enable signal. - 5 pre-ramp delay the device requires a minimum delay period following an enable signal and prior to ramping its output, as described in ?soft-start delay and ramp times? on page 17. -
ZL9006M 17 fn7959.0 march 5, 2013 soft-start delay and ramp times it may be necessary to set a delay when an enable signal is received until the output voltage starts to ramp to its target value. in addition, the designer may wish to precisely set the time required for v out to ramp to its target value after the delay period has expired. these features may be used as part of an overall inrush current manageme nt strategy or to precisely control how fast a load ic is turned on. the ZL9006M gives the system designer several options for precisely and independently controlling both the delay and ramp time periods. the soft-start delay period begins when the en pin is asserted and ends when the delay time expires. the soft-start ramp timer enables a precisely controlled ramp to the nominal v out value that begins once the delay period has expired. the ramp-up is guaranteed monotonic and its slope may be precisely set using the ss pin. the soft-start delay and ramp times can be set to a custom value by pin-strapping or connecting a re sistor from the ss pin to sgnd using the appropriate resistor value from table 6. see ?input undervoltage lockout? on page 19 for further explanation of uvlo setting using ss pin. the value of this resistor is measured upon start-up or restore and will not change if the resistor is varied after power has been applied to the ZL9006M. table 6. soft-start pin-strap/resistor settings with the ss pin open, the defaul t value for delay time and ramp time is 5ms. the soft-start delay and ramp times are set to custom values via the i 2 c/pmbus interface. when the delay time is set to 0ms, the device begins its ramp-up after the internal circuitry has initialized (approximately 2ms). when the soft-start ramp period is set to 0ms, the output ramps up as quickly as the output load capacitance and loop settings allow. it is generally recommended to set the soft-start ramp to a value greater than 500s to prevent inadvertent fault conditions due to excessive inrush current. the ZL9006M has a minimum t on_delay requirement that is a function of the operating mode. table 7 shows the different mode configurations and the minimum t on_delay required for each mode. current sharing is configured with the ishare_config pmbus command, auto compensation is configured with the auto_comp_config command, and standby mode is configured as low power with the user_config command. see application note an2033 for details. resistor programming on the ss pin with a delay time of 20ms can be used to satisfied the minimum t on_delay of 15ms. power-good the ZL9006M provides a power-good (pg) signal that indicates the output voltage is within a sp ecified tolerance of its target level and no fault condition exists . by default, the pg pin asserts if the output is within +15/-10% of the target voltage. these limits and the polarity of th e pin may be changed via the i 2 c/pmbus interface. see application note an2033 for details. a pg delay period is defined as the time when all conditions within the ZL9006M for asserting pg are met, to when the pg pin is actually asserted. this feature is commonly used instead of using an external reset controller to control external digital logic. by default, the ZL9006M pg delay is set to 1ms, and may be changed using the i 2 c/pmbus as described in application note an2033 . by default, the ZL9006M pg delay is set equal to the soft-start ramp time setting. therefore, if the soft-start ramp time is set to 6ms, the pg delay is set to 6ms. the pg delay may be set independently of the soft-start ramp using the i 2 c/pmbus as described in application note an2033 . if auto comp is enabled, the pg timing is further controlled by the pg assert parameter, as de scribed in ?loop compensation? on page 18. r ss (k ? ) delay time (ms) ramp time (ms) uvlo (v) low 5 2 4.5 open 5 5 high 10 10 10 5 2 3 11 5 5 12.1 10 13.3 20 14.7 5 10 16.2 10 17.8 20 19.6 5 2 4.5 21.5 10 23.7 5 5 26.1 10 28.7 20 31.6 5 10 34.8 10 38.3 20 42.2 5 2 10.8 46.4 10 51.1 5 5 56.2 10 61.9 20 68.1 5 10 75 10 82.5 20 table 7. minimum t on_delay vs operating mode current sharing autocomp low-power standby min. t on_delay (ms) x disabled false 5 disabled enabled false 5 disabled x true 10 enabled disabled true 15 enabled enabled x 15
ZL9006M 18 fn7959.0 march 5, 2013 switching frequency and pll the ZL9006M incorporates an internal phase-locked loop (pll) to clock the internal circuitry. the pll can be driven by an external clock source connected to the sync pin. when using the internal oscillator, the sync pin can be configured as a clock source for other zilker labs devices. with the fc0 pin,the sync pin can be configured as input, auto detect, and output. pinstrap resistor setting to ?input? mode is applicable for member devices used in current sharing mode only. when multiple modules are used together, connecting the sync pins together will force all devices to synchronize with each other. one device must set its sync pin as an output and the remaining devices must have their sync pins set as auto detect. sync auto detect in auto detect mode, the module will check for a clock signal on the sync pin immediately after power-up. in this case, the incoming clock signal must be in the range of 300khz to 1.0mhz and must be stable within 10s after v25 rises above 2.25v. if the device is in low power mode, it will check for a clock signal on the sync pin immediately after en goes true. in this case, the incoming clock signal must be in range and stable before en goes true. if a clock signal is present, the ZL9006M's oscillator will then synchronize with the rising edge of the external clock. if no incoming cloc k signal is present, the ZL9006M will configure the switching frequency according to an external resistor, r sync , connected between sync and sgnd using table 8, given that fc0 used pin-strap or has a resistor r fc0 in the range of 10-13.3k ? . when fc0 is open, or used with resistor settings in the range, the switching frequency of the ZL9006M is set to a default of 615khz. the module will only read the sync pin connection during the first start-up sequence; changes to sync pin connections will not affect f sw until the power (vdd) is cycled off and on. frequency modifications without restarting the v dd power can disable the sync auto detect function. sync output when the sync pin is configured as an output via i 2 c, the device will run from its internal oscillator and will drive the resulting internal oscillator signal onto the sync pin so other devices can be synchronized to it. the sync pin will not be checked for an incoming clock signal while in this mode. when fc0 is used with resistor settings in the range of 14.7-31.6k ? , the ZL9006M drives the sync pin with frequency as described in table 9, and will ignore any resistor settings on the sync pin. similarly, when fc0 is used with a selected value of resistors in the range of 46.4-178k ? , the ZL9006M operates in current sharing mode with the sync pin providing clock out. when fc0 is used with resistor settings in the range of 34.8 to 42.2k ? , ZL9006M will first read the sync pin connection, and drives the sy nc pin with the frequency described in table 8. in this mode, the sync pin should not be pin strapped to low or high (voltage source). it is recommended to connect a buffer with high impedance, as seen by the sync pin of the module providing the clock out, to subsequently drive the sync pin of other devices. sync setting via i 2 c consideration the switching frequency can be set to any value between 300khz and 1.0mhz using the i 2 c/pmbus interface. the available frequencies below 1.0mhz are defined by f sw = 8mhz/n, where the whole number n is 8 n 27. see application note an2033 for details. if a value other than f sw = 8mhz/n is entered using a pmbus command, the internal circuitry will select the valid switching frequency value that is closest to the entered value. for example, if 810khz is entered, the device will select 800khz (n = 10). loop compensation the ZL9006M operates as a voltage-mode synchronous buck controller with a fixed frequency pwm scheme. the module is internally compensated via the i 2 c/pmbus interface. the auto compensation feature measures th e characteristics of the power train and calculates the proper tap coefficients, and can be configured according to an external resistor, r fc0 , connected between fc0 and sgnd in table 9. if the device is configured to store auto comp values, the calculated compensation values will be saved in the auto comp store and may be read back through the pid_taps command. if repeat mode is enabled, the first auto comp results after the first ramp will be stored; the values calculated periodically are not stored in the auto comp store. when compensation values are saved in the auto comp store, the device will use those compensation values on subsequent ramps. in repeat mode, the latest auto comp results will alwa ys be used during operation. stored auto comp results can only be cleared by disabling auto comp store, which is not permitted while the output is enabled. however, sending the autocomp_control command while enabled in store mode will cause the next results to be stored, overwriting previously stored values. if auto compensation is disabled, the device will use the compensation parameters that are stored in the default_store or user_store. if the pg assert parameter is set to "use pg delay," pg will be asserted according to the power_good_delay command, after which auto comp will begin. when auto comp is enabled, the user must not program a power-good delay that will expire before the ramp is finished. if pg assert is set to "after auto comp," pg will be asserted im mediately after the first auto comp cycle completes (power_good_delay will be ignored). the routine can be set via the i 2 c/pmbus interface to execute one time after ramp or periodically while regulating, and have table 8. switching frequency pin-strap/resistor settings sync pin/ r sync (k ? ) f sw (khz) sync pin/ r sync (k ? ) f sw (khz) low 400 23.7 471 open 615 26.1 533 high 800 28.7 571 14.7 296 31.6 615 16.2 320 34.8 727 17.8 364 38.3 800 19.6 400 46.4 889 21.5 421 51.1 1000
ZL9006M 19 fn7959.0 march 5, 2013 either pg assert behavior descri bed earlier. note that the auto compensation feature requires a minimum t on_delay as described in ?soft-start delay and ramp times? on page 17. the auto comp gain control scales the auto comp results to allow a trade-off between transi ent response and steady-state duty cycle jitter. a setting of 100% will provide the fastest transient response while a setting of 10% will produce the lowest jitter. with resistor settings, auto co mpensation can only be set to execute one time after ramp with option to store auto comp values. with auto compensation disabled, pg is asserted according to power_good_delay. with auto compensation executed once and auto comp values not stored, pg is asserted after auto compensation is complete at every start-up event. with auto compensation executed once and auto comp values stored, pg is asserted after auto compensation is complete at the first start-up event, an d is asserted according to power_good_delay for subsequent start-up event along with using the stored auto comp values from the first start-up. by default with fc0 open, auto co mpensation is configured to execute one time after ramp with 70% auto comp gain, pg asserted immediately after the first auto comp cycle completes, and auto comp values not stored. note that if auto comp is enabled, for best results v in must be stable before auto comp begins, as shown in equation 3. the auto compensation function can also be configured via the auto_comp_config command and controlled using the auto_comp_control command over the i 2 c/pmbus interface. please refer to application note an2033 for further details. adaptive diode emulation adaptive diode emulation mode tu rns off the low-side fet gate drive at low load currents to prevent the inductor current from going negative, reducing the ener gy losses and increasing overall efficiency. diode emulation is available to single-phase devices only. note: the overall bandwidth of the device may be reduced when in diode emulation mode. disablin g the diode emulation prior to applying significant load steps is recommended. input undervoltage lockout the input undervoltage lockout (uvlo) prevents the ZL9006M from operating when the input falls below a preset threshold, indicating the input supply is out of its specified range. the uvlo threshold (v uvlo ) can be set between 2.85v and 16v using the i 2 c/pmbus interface. once an input undervoltage fault condition occurs, the device can respond in a number of ways, as follows: 1. continue operating without interruption. 2. continue operating for a given delay period, followed by shutdown if the fault still exists. the device remains in shutdown until instructed to restart. 3. initiate an immediate shutdown until the fault is cleared. the user can select a specific number of retry attempts. the default response from a uvlo fault is an immediate shutdown of the module. the cont roller continuously checks for the presence of the fault condition. if the fault condition is no longer present, the ZL9006M is re-enabled. please refer to application note an2033 for details on how to configure the uvlo threshold or to select specific uvlo fault response options via the i 2 c/pmbus interface. table 9. fc0 pin-strap/resistor settings fc0 pin/ r fc0 (k ? ) autocomp config sync pin config sync override ac single/ disable ac gain store values low auto comp disabled auto detect open single 70 not stored high store in flash 10 single 50 not stored auto detect 11 store in flash 12.1 90 not stored 13.3 store in flash vin vin nom --------------------- in% () 100% 1 256 vout ? vin nom ----------------------------- + -------------------------------------- - (eq. 3) 14.7 auto comp disabled output 400khz 16.2 single 70 not stored 17.8 store in flash 19.6 auto comp disabled 615khz 21.5 single 70 not stored 23.7 store in flash 26.1 auto comp disabled 800khz 28.7 single 70 not stored 31.6 store in flash 34.8 auto comp disabled depend on rsync 38.3 single 70 not stored 42.2 store in flash table 9. fc0 pin-strap/resist or settings (continued) fc0 pin/ r fc0 (k ? ) autocomp config sync pin config sync override ac single/ disable ac gain store values
ZL9006M 20 fn7959.0 march 5, 2013 output overvoltage protection the ZL9006M offers an internal output overvoltage protection circuit that can be used to protect sensitive load circuitry from being subjected to a voltage higher than its prescribed limits. a hardware comparator is used to compare the actual output voltage (seen at the fb+ pin) to a threshold set to 15% higher than the target output voltage (the default setting). if the fb+ voltage exceeds this threshold, the pg pin de-asserts, and the controller can then respond in a number of ways, as follows: 1. initiate an immediate shutdown until the fault is cleared. the user can select a specific number of retry attempts. 2. turn off the high-side and turn on the low-side mosfets until the device attempts a restart. the default response from an over voltage fault is to immediately shut down. the controller continuously checks for the presence of the fault condition, and when the fault condition no longer exists, the device is re-enabled. for continuous overvoltage protection when operating from an external clock, the only allo wed response is an immediate shutdown. please refer to application note an2033 for details on how to select specific overvoltage fault response options via i 2 c/pmbus. output pre-bias protection an output pre-bias condition exists when an externally applied voltage is present on a power supply?s output before the power supply?s control ic is enabled. certain applications require that the converter not be allowed to si nk current during start-up if a pre-bias condition exists at the output. the ZL9006M provides pre-bias protection by sampling the output voltage prior to initiating an output ramp. if a pre-bias voltage lower than th e target voltage exists after the pre-configured delay period has expired, the target voltage is set to match the existing pre-bias voltage, and both drivers are enabled. the output voltage is then ramped to the final regulation value at the preconfigured ramp rate. the actual time the output takes to ramp from the pre-bias voltage to the target voltage varies, depending on the pre-bias voltage, but the total time elap sed from when the delay period expires and when the output reaches its target value will match the pre-configured ramp time (see figure 21). if a pre-bias voltage higher than the target voltage exists after the pre-configured delay period has expired, the target voltage is set to match the existing pre-bias voltage, and both drivers are enabled with a pwm duty cycle that would ideally create the pre-bias voltage. once the pre-configured soft-start ramp period has expired, the pg pin is asserted (assuming the pre-bias voltage is not higher than the overvoltage limit). the pwm then adjusts its duty cycle to match the original target voltage, and the output ramps down to the preconfigured output voltage. if a pre-bias voltage higher than the overvoltage limit exists, the device does not initiate a turn-on sequence and declares an overvoltage fault condition to exist. in this case, the device responds based on the output overvoltage fault response method that has been selected. see ?output overvoltage protection? on page 20 for response options due to an overvoltage condition. note that pre-bias protection is not offered for current sharing groups that also have tracking enabled. v dd must be the same voltage as v in for proper prebias start-up in single module operation. output overcurrent protection the ZL9006M can protect the power supply from damage if the output is shorted to ground or if an overload condition is imposed on the output. the following ov ercurrent protection response options are available: 1. initiate a shutdown and attempt to restart an infinite number of times with a preset delay period between attempts. 2. initiate a shutdown and attempt to restart a preset number of times with a preset delay period between attempts. 3. continue operating for a given delay period, followed by shutdown if the fault still exists. 4. continue operating through th e fault (this could result in permanent damage to the power supply). 5. initiate an immediate shutdown. the default response from an ov ercurrent fault is an immediate shutdown of the controller. the co ntroller continuously checks for the presence of the fault condition, and if the fault condition no longer exists, the device is re-enabled. please refer to application note an2033 for details on how to select specific overcurrent fault response options via i 2 c/pmbus. figure 21. output responses to pre-bias voltages
ZL9006M 21 fn7959.0 march 5, 2013 thermal overload protection the ZL9006M includes a thermal sensor that continuously measures the internal temperat ure of the module and shuts down the controller when the temperature exceeds the preset limit. the default temperature limit is set to +125c in the factory, but the user may set the limit to a different value if desired. see application note an2033 for details. note that setting a higher thermal limit via the i 2 c/pmbus interface may result in permanent damage to the controller. once the module has been disabled due to an inte rnal temperature fault, the user may select one of several faul t response options as follows: 1. initiate a shutdown and attempt to restart an infinite number of times with a preset delay period between attempts. 2. initiate a shutdown and attempt to restart a preset number of times with a preset delay period between attempts. 3. continue operating for a given delay period, followed by shutdown if the fault still exists. 4. continue operating through th e fault (this could result in permanent damage to the power supply). 5. initiate an immediate shutdown. if the user has configured the module to restart, the controller waits the preset delay period (if configured to do so) and then checks the module temperature. if the temperature has dropped below a threshold that is approximately +15c lower than the selected temperature fault limit, the controller attempts to re-start. if the temperature stil l exceeds the fault limit, the controller waits the preset delay period and retries again. the default response from a temp erature fault is an immediate shutdown of the module. the cont roller continuously checks for the fault condition, and once th e fault has cleared, the ZL9006M is re-enabled. please refer to application note an2033 for details on how to select specific temperature fault response options via i 2 c/pmbus. voltage tracking numerous high performance sy stems place stringent demands on the order in which the power supply voltages are turned on. this is particularly true when powering fpgas, asics, and other advanced processor devices that require multiple supply voltages to power a single die. in most ca ses, the i/o interface operates at a higher voltage than the core and therefore the core supply voltage must not exceed the i/o supply voltage according to the manufacturers' specifications. voltage tracking protects these sensitive ics by limiting the differential voltage between multiple power supplies during the power-up and power down sequence. the ZL9006M integrates a lossless tracking scheme that allows its output to track a voltage that is applied to the vtrk pin with no external components required . the vtrk pin is an analog input that, when tracking mode is enabled, configures the voltage applied to the vtrk pin to act as a reference for the device?s output regulation. figure 22 illustrates the typical connection of two tracking modules. the ZL9006M offers two modes of tracking as follows, and can be configured according to an external resistor, r ss , connected between ss and sgnd in table 10 or via i 2 c/pmbus. the t on _ delay time is set to 5ms, and t off_delay time is set to 35ms. the ramp time is set to 2ms, but can track to a slower ramp time, i.e., >2ms. 1. coincident . this mode configures the module to ramp its output voltage at the same rate as the voltage applied to the vtrk pin. two options are available for this mode: - track at 100% v out limited. member rail tracks the reference rail and stops when the member reaches its target voltage (figure 23a). - track at 100% vtrk limited. member rail tracks the reference at the instantaneous voltage value applied to the vtrk pin (figure 23b). 2. ratiometric . this mode configures the module to ramp its output voltage at a rate that is a percentage of the voltage applied to the vtrk pin. the default setting is 50%, but an external resistor string may be used to configure a different tracking ratio: -track at 50% v out limited. member rail tracks the reference rail and stops when the member reaches 50% of the target voltage (figure 24a). - track at 50% vtrk limited. member rail tracks the reference at the instantaneous voltage value applied to the vtrk pin until the member rail reaches 50% of the reference rail voltage, or if the member is configured to less than 50% of the reference the member will achieve its configured target (figure 24b). the master module device in a tracking group is defined as the device that has the highest target output voltage within the group. this master device will control the ramp rate of all tracking devices and is not configured for tracking mode. a delay of at least 6ms must be configured into the master device, and the user may also configure a spec ific ramp rate. any device that is configured for tracking mode will ignore its soft-start delay and its output will take on the turn-on/turn-off characteristics of the reference voltage present at the vtrk pin. all of the enable pins in the tracking group must be connected together and driven by a single logic source. tracking is configured via the i 2 c/pmbus interface by using the track_config pmbus command. please refer to application note an2033 for further details on configuring tracking mode using pmbus. table 10. tracking resistor settings r ss (k ? ) track ratio (%) upper track limit ramp-up/down behavior 90.9 100 limited by target output does not decrease before pg 100 output always follows vtrk 110 limited by vtrk output does not decrease before pg 121 output always follows vtrk 133 50 limited by target output does not decrease before pg 147 output always follows vtrk 162 limited by vtrk output does not decrease before pg 178 output always follows vtrk
ZL9006M 22 fn7959.0 march 5, 2013 when the ZL9006M is configured to the voltage tracking mode, the voltage applied to the vtrk pin acts as a reference for the member device(s) output re gulation. when the auto compensation algorithm is used the soft-start values (rise/fall times) are used to calculate the loop gain used during the turn-on/turn-off ramps. if current sharing is used, constrain the rise/fall time between 5 and 20m s to ensure current sharing while ramping. tracking groups in a tracking group, the device configured to the highest voltage within the group is defined as the reference device. the device(s) that track the reference is called member device(s). the reference device will control the ramp delay and ramp rate of all tracking devices and is not plac ed in the tracking mode. the reference device is configured to the highest output voltage for the group and all other device(s)? output voltages are meant to track and never exceed the reference device output voltage. the reference device must be configured to have a minimum time-on delay and time-on rise as shown in equation 4: this delay allows the member device(s) to prepare their control loops for tracking followin g the assertion of enable. the member device time-off delay has been redefined to describe the time that the vtrk pin will follow the reference voltage after enable is de-asserted. the delay setting sets the timeout for the member's output voltage to turn off in the event that the reference output voltage does not achieve zero volts. the member device(s) must have a minimum time-off delay of as shown in equation 5: all of the enable pins must be connected together and driven by a single logic source or a p mbus broadcast enable command may be used. the configuration settings for figures 23 and 24 are shown below in tables 11 through 14. in each case the reference and member rise times are set to the same value. figure 22. pmbus trac king configuration zl zl vout vtrk c out r sda scl sda scl c out m reference member vout_r vout_m figure 23. coincident tracking track @ 100% vout limited vref > vmem en 0 0 en ~ ~ ~ ~ toff dly ton d ly vmem vr ef track @ 100% vtrk limited vref = vmem ~ ~ toff dly ton dly vr ef vmem coi n ci den t tracki ng vref =1.8 v vmem=0. 9v vref =1.8 v vmem=1.8v a. b. figure 24. ratiometric tracking 0 en en 0 track @ 50% vout li m ited vref = 1.8v vm em = 0. 9v ~ ~ ~ ~ toff dl y ton d ly vmem vref track @ 50% vtrk li m ited vref = 1.8v vm em = 0.9v rat io metri c trac ki ng vref =1.8v vmem=0. 9v ~ ~ ~ ~ ton d ly toff dl y vref vmem vref =1.8v vmem=0. 9v a. b. table 11. tracking configuration figure 23a rail v out (v) t on dly (ms) t on rise (ms) t off dly (ms) t off fall (ms) mode reference 1.8 15 5 5 5 tracking disabled member 0.9 5 5 15 5 100% v out limited table 12. tracking configuration figure 23b rail v out (v) t on dly (ms) t on rise (ms) t off dly (ms) t off fall (ms) mode reference 1.8 15 5 5 5 tracking disabled member 1.8 5 5 15 5 100% v trk limited table 13. tracking configuration figure 24a rail v out (v) t on dly (ms) t on rise (ms) t off dly (ms) t off fall (ms) mode reference 1.8 15 5 5 5 tracking disabled member 0.9 5 5 15 5 50% v out limited table 14. tracking configuration figure 24b rail v out (v) t on dly (ms) t on rise (ms) t off dly (ms) t off fall (ms) mode reference 1.8 15 5 5 5 tracking disabled member 1.8 5 5 15 5 50% v trk limited t on_dly (ref) > t on_dly (mem) + t on_rise (ref) + 5ms > t on_dly (mem) + 6ms (eq. 4) t off_dly (mem) > t off_dly (ref) + t off_fall (ref) + 5ms (eq. 5)
ZL9006M 23 fn7959.0 march 5, 2013 voltage margining the ZL9006M offers a simple means to vary its output higher or lower than its nominal voltage setting in order to determine whether the load device is capable of operating over its specified supply voltage range. the mgn command is set through the i 2 c/pmbus interface. the module?s output will be forced higher than its nominal set point when the mgn command is set high, and the output will be forced lower than its nominal set point when the mgn command is set low. default margin limits of v nom 5% are pre-loaded in the factory, but the margin limits can be modified through the i 2 c/pmbus interface to as high as v nom + 10% or as low as 0v, where v nom is the nominal output voltage set point determined by the v1 pin. the margin limits and the mgn command can both be set individually through the i 2 c/pmbus interface. additionally, the transition rate between the nomi nal output voltage and either margin limit can be configured through the i 2 c interface. please refer to application note an2033 for further instructions on modifying the margin ing configurations. digital-dc bus the digital-dc communications (ddc) bus is used to communicate between zilker labs digital-dc modules and devices. this dedicated bus prov ides the communication channel between devices for features such as sequencing, fault spreading, and current sharing. the ddc pin on all digital-dc devices in an application should be connected together. a pull-up resistor is required on the ddc bu s in order to guarantee the rise time as shown in equation 6: where r pu is the ddc bus pull-up resistance and c load is the bus loading. the pull-up resistor may be tied to an external 3.3v or 5v supply as long as this voltage is present prior to or during device power-up. as a rule of thumb, each device connected to the ddc bus presents approximately 10pf of capacitive loading, and each inch of fr4 pcb trace introduces approximately 2pf. the ideal design uses a central pull-up resistor that is well- matched to the total load capa citance. the minimum pull-up resistance should be limited to a value that enables any device to assert the bus to a voltage that ensures a logic 0 (typically 0.8v at the device monitoring point), given the pull-up voltage and the pull-down current capability of the ZL9006M (nominally 4ma). output sequencing a group of digital-dc modules or devices may be configured to power-up in a predetermined sequence. this feature is especially useful when powering advanced processors, fpgas, and asics that require one supply to reac h its operating voltage prior to another supply reaching its operating voltage in order to avoid latch-up. multi-device sequencing can be achieved by configuring each device through the i 2 c/pmbus interface. multiple device sequencing is configured by issuing pmbus commands to assign the preceding device in the sequencing chain as well as the device that follows in the sequencing chain. the enable pins of all devices in a sequencing group must be tied together and driven high to initiate a sequenced turn-on of the group. enable must be driven low to initiate a sequenced turnoff of the group. refer to application note an2033 for details on sequencing via the i 2 c/pmbus interface. fault spreading digital dc modules and devices can be configured to broadcast a fault event over the ddc bus to the other devices in the group. when a non-destructive fault occurs and the device is configured to shut down on a fault, the device shuts down and broadcasts the fault event over the ddc bus. the other devices on the ddc bus shut down together, if configured to do so, and attempt to re-start in their prescribed order, if configured to do so. monitoring via i 2 c/pmbus a system controller can monitor a wide variety of different ZL9006M system parameters through the i 2 c/pmbus interface. the device can monitor for fault conditions by monitoring the salrt pin, which will be pulled low when any number of pre-configured fault conditions occur. the module can be monitored continuously for any number of power conversion parameters including the following: ?input voltage ?output voltage ?output current ? internal temperature ? external temperature ? switching frequency ? duty cycle the pmbus host should respond to salrt as follows: 1. zl device pulls salrt low. 2. pmbus host detects that salrt is now low, performs transmission with alert respon se address to find which zl device is pulling salrt low. 3. pmbus host talks to the zl de vice that has pulled salrt low. the actions that the host performs are up to the system designer. if multiple devices are faulting, salrt will still be low after doing the above steps and will require transmission with the alert response address repeatedly until all faults are cleared. please refer to application note an2033 for details on how to monitor specific parameters via the i 2 c/pmbus interface. temperature monitoring using the xtemp pin the ZL9006M supports measurement of an external device temperature using either a thermal diode integrated in a processor, fpga or asic, or us ing a discrete diode-connected 2n3904 npn transistor. figure 25 illustrates the typical connections required. rise time r pu ? c load 1 s = (eq. 6)
ZL9006M 24 fn7959.0 march 5, 2013 snapshot parameter capture the ZL9006M offers a special feat ure that enables the user to capture parametric data during normal operation or following a fault. the snapshot functionality is enabled by setting bit 1 of misc_config to 1. see an2033 for details on using snapshot in addition to the parameters supported. the snapshot feature enables the user to read parameters via a block read transfer through the pmbus. this can be done during normal op eration, although it should be noted that reading the 22 bytes occupies the pmbus for some time. the snapshot_control command enables the user to store the snapshot parameters to flash memory in response to a pending fault, as well as to read the stored data from flash memory after a fault has occurred. table 15 describes the usage of this command. automatic writes to flash memory following a fault are triggered when any faul t threshold level is exceeded, provided that the specific fault?s response is to shut down (writing to flash memory is not allowed if the device is configured to re-try following the specific fault condition). it should also be noted that the module?s v dd voltage must be maintained during the time when the controller is writing the data to flash memory; a process that requires between 700s to 1400s depending on whether th e data is set up for a block write. undesirable results may be observed if the device?s v dd supply drops below 3.0v during this process. if the module experiences a fault and power is lost, the user can extract the last snapshot parameters stored during the fault by writing a 1 to snapshot_control (transfers data from flash memory to ram) and then issuing a snapshot command (reads data from ram via pmbus). non-volatile memory and device security features the ZL9006M has internal non-volatile memory where user configurations are stored. integr ated security measures ensure that the user can only restore the module to a level that has been made available to them. during the initialization process, the ZL9006M checks for stored values contained in its internal non-volatile memory. the ZL9006M offers two internal memory storage units that are accessible by the user as follows: 1. default store: the ZL9006M has a default configuration that is stored in the default store in the controller. the module can be restored to its default settings by issuing a restore_default_all command over the pmbus. 2. user store: the user can modify certain power supply settings as described in this data sheet. the user stores their configuration in the user store. please refer to application note an2033 for details on how to set specific security measures via the i 2 c/pmbus interface. layout guide to achieve stable operation, low losses, and good thermal performance, some layout considerations are necessary (figure 26). ? establish a continuous ground plane connecting the dgnd pin and pgnd pin f10 with via directly to the ground plane. ? establish sgnd island connect ing (pad 3, pin c1) and the return path of analog signals and resistor programming pin signals. ? establish pgnd island connecting pgnd (pad 2, 5, pin f10). ? make a single point connection between sgnd and pgnd islands. ? place a high frequency ceramic capacitor between (1) vin and pgnd (pad 2) (2) vout and pgnd (pad 5) as close to the module as possible to minimize high frequency noise. high frequency ceramic capacitors close to the module between vout and pgnd will help to minimize noise at the output ripple. ? use large copper areas for power path (vin, pgnd, vout, sw) to minimize conduction loss and thermal stress. also, use multiple vias to connect the power planes in different layers. ? connect remote sensed traces fb+ and fb- to the regulation point to achieve a tight output voltage regulation, and keep them in parallel. route a trace from fb- to a location near the load ground, and a trace from fb+ to the point-of-load where the tight output voltage is desired. ? avoid routing any sensitive signal traces, such as the vout, fb+, fb- sensing point near the sw pad. table 15. snapshot_control command data value description 1 copies current snapshot values from flash memory to ram for immediate access using snapshot command. 2 writes current snapshot values to flash memory. only available when device is disabled. zl sgnd xtemp discrete npn 2n3904 zl sgnd xtemp embedded thermal diode p fpga dsp asic 100 pf 100 pf figure 25. external temperature monitoring
ZL9006M 25 fn7959.0 march 5, 2013 thermal considerations experimental power loss curves along with ja from thermal modeling analysis can be used to evaluate the thermal consideration for the module. the derating curves are derived from the maximum power allowed while maintaining the temperature below the maximum junction temperature of +125c. in actual application, other heat sources and design margin should be considered. package description the structure of ZL9006M belongs to the high density array (hda) package. this kind of package has advantages, such as good thermal and electrical conductivity, low weight and small size. the hda package is applicable for surface mounting technology. the ZL9006M contains several types of devices, including resistors, capacitors, inductors and control ics. the ZL9006M is a copper lead-frame based package with exposed copper thermal pads, which have good electrical and thermal conductivity. the copper lead frame and multi component assembly is overmolded with polymer mold compound to protect these devices. the package outline and typical pcb layout pattern design and typical stencil pattern design ar e shown in the package outline drawing y32.17.2x11.45 on page 27 . the module has a small size of 17.2mm x 11.45mm x 2.5mm. fi gure 27 shows typical reflow profile parameters. these guidelin es are general design rules. users could modify parameters according to their application. pcb layout pattern design the bottom of the ZL9006M is a le ad-frame footprint, which is attached to the pcb by surface mounting process. the pcb layout pattern is shown in the package outline drawing y32.17.2x11.45 on page 27. the pcb layout pattern is essentially 1:1 with the hda ex posed pad and i/o termination dimensions. the thermal lands on the pcb layout should match 1:1 with the package exposed die pads. thermal vias a grid of 1.0mm to 1.2mm pitch thermal vias, which drops down and connects to buried copper plane(s), should be placed under the thermal land. the vias should be about 0.3mm to 0.33mm in diameter with the barrel plated to about 1.0 ounce copper. although adding more vias (by de creasing via pitch) will improve the thermal performance, diminishing returns will be seen as more and more vias are added. simply use as many vias as practical for the thermal land size and your board design rules allow. stencil pattern design reflowed solder joints on the perimeter i/o lands should have about a 50m to 75m (2mil to 3m il) standoff height. the solder paste stencil design is the first step in developing optimized, reliable solder joins. stencil aperture size to land size ratio should typically be 1:1. the aperture width may be reduced slightly to help prevent solder bridging between adjacent i/o lands. to reduce solder paste volume on the la rger thermal lands, it is recommended that an array of sm aller apertures be used instead of one large aperture. it is reco mmended that the stencil printing area cover 50% to 80% of the pcb layout pattern. a typical solder stencil pattern is shown in the package outline drawing y32.17.2x11.45 on page 27. the gap width pad to pad is 0.6mm. the user should consider the symmetry of the whole stencil pattern when designing its pads. a laser cut, stainless steel stencil with electropolished trapezoidal walls is recommended. electropolishing ?smooths? the aperture walls resulting in reduced surface friction and better paste release which reduces voids. using a trapezoidal section aperture (tsa) also promotes paste release and forms a "brick like" paste deposit that assists in firm component placement. a 0.1mm to 0.15mm stencil thickness is recommended for this large pitch (1.3mm) hda. sgnd pgnd pgnd pgnd dgnd sgnd vin sw vout vr pgnd fb+ fb- sgnd kelvin sensing lines figure 26. recommended layout
ZL9006M 26 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7959.0 march 5, 2013 for additional products, see www.intersil.com/en/products.html reflow parameters due to the low mount height of the hda, "no clean" type 3 solder paste per ansi/j-std-005 is recommended. nitrogen purge is also recommended during reflow. a system board reflow profile depends on the thermal mass of the entire populated board, so it is not practical to define a specific soldering profile just for the hda. the profile given in figure 27 is provided as a guideline, to be customized for varying manufacturing practices and applications. about intersil intersil corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management semiconductors. the company's products addr ess some of the fastest growing markets wi thin the industrial and infrastructure, personal computing and high-end consumer markets. for more inform ation about intersil or to find out how to become a member of our winning team, visit our website and career page at www.intersil.com . for a complete listing of applications, re lated documentation and related parts, plea se see the respective product information page. also, please check the product information page to ensure that you have the most updated datasheet: ZL9006M to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff reliability reports are available from our website at: http://rel.intersil.com/reports/search.php figure 27. typical reflow profile 0300 100 150 200 250 350 0 50 100 150 200 250 300 temperature (c) duration (s) slow ramp (3c/s max) and soak from +150c to +200c for 60s~180s ramp rate 1.5c from +70c to +90c peak temperature ~+245c; typically 60s-150s above +217c keep less than 30s within 5c of peak temp. revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change march 5, 2013 fn7959.0 initial release
ZL9006M 27 fn7959.0 march 5, 2013 package outline drawing y32.17.2x11.45 32 i/o 17.2mm x 11.45mm x 2.5mm hda module rev 1, 11/12 bottom view side view top view detail a detail b 1.0mmx1.0mm represents the basic land grid pitch. 2. all dimensions are in millimeters. 1. notes: ?27? is the total number of i/o (excluding large pads). all 27 i/o?s are centered in a fixed row and column matrix at 1.0mm pitch bsc. dimensioning and tolerancing per asme y14.5m-1994. tolerance for exposed dap edge location dimension on page 2 is 0.1mm. 3. 4. 5. terminal tip 3 see detail b c = 0.35 see detail a datum a datum b 11.45 17.20 0.025 max 2.50 max 7.00 10.400.15 10.00 0.900.10 16.500.15 0.180.10 0.95 1.00 27x(0.600.05) 1.00 0.550.10 0.550.10 27x(0.600.05) 1.00 2.00 0.10 c seating plane 2x terminal #a1 index area 2x a b pin a1 indicator 0.10 c 0.10 c k l 3 9 10 6 8 7 4 5 e d j h g f c b a 2 1 0.10 c a b 0.10 c a b 0.10 c 0.08 c 0.10 c a b 0.05 c 3
ZL9006M 28 fn7959.0 march 5, 2013 centerline position details for the 5 exposed daps size details for the 5 exposed daps bottom view bottom view 0.38 4.20 4.38 3.88 1.48 0.46 5.45 7.60 4.60 4.35 7.95 4.75 0.60 4.00 1.80 2.00 4.80 1.85 3.87 5.40 1.30 3.30 3.20 3.20 a 6 7 notes: 6. shown centerline measurement of 0.46mm applies to ZL9006M module. for the zl9010m module, this measurement is 0.33mm. all oth er measures identical for both the ZL9006M and zl9010m modules. 7. shown pad edge measurement of 3.87mm ap plies to ZL9006M module. for the zl9010m modu le, this measurement is 3.60mm. all other measurements are identical for both the ZL9006M and zl9010m modules.
ZL9006M 29 fn7959.0 march 5, 2013 terminal and pad edge details bottom view 2.75 2.75 5.73 1.53 3.28 5.13 2.39 1.98 8.15 0.00 0.13 1.48 0.48 1.23 3.48 2.48 5.73 5.28 8.60 8.25 7.65 6.25 2.95 2.75 6.95 6.75 2.75 0.35 1.25 0.00 0.25 0.65 1.35 0.75 2.35 1.75 0.00 1.35 0.75 2.35 1.75 7.75 7.75 5.35 3.35 4.75 5.75 5.95 7.35 6.75 5.35 3.75 3.35 4.75 4.35 6.35 5.75 7.35 6.75 1.13 1.53 2.13 2.53 3.13 3.53 4.13 4.53 5.13 8.35 0.00 5.48 4.88 3.48 4.48 3.88 2.88 2.48 1.88 1.48 0.88 0.48 0.53 0.13 8.60 8.35 7.75 notes: 8. shown edge pad measurement of 2.39mm appl ies to ZL9006M module. for the zl9010m modul e, this measurement is 2.13mm. all other measurements are identical for both the ZL9006M & zl9010m modules. 8
ZL9006M 30 fn7959.0 march 5, 2013 2.90 2.90 3.11 4.11 5.11 3.54 4.54 5.73 7.77 8.60 8.34 7.34 2.34 4.77 6.77 5.77 4.95 6.34 5.34 5.75 2.77 3.34 3.75 4.75 3.95 2.95 1.77 0.77 1.34 0.00 3.89 4.89 5.73 2.89 1.89 0.89 1.11 1.78 0.54 7.77 8.60 2.46 1.46 0.46 0.11 1.54 2.11 2.54 0.98 0.22 1.02 4.46 5.46 3.46 8.34 7.34 2.34 2.77 3.77 4.77 5.77 6.77 6.34 5.34 3.34 4.34 1.23 0.66 0.23 0.34 0.77 1.77 1.34 0.00 5.10 4.00 4.90 3.10 3.80 5.30 6.00 7.10 6.20 7.30 5.73 4.97 3.42 8.60 8.00 7.75 3.90 5.10 5.60 6.60 4.10 6.10 5.40 7.05 8.15 8.60 5.73 1.58 3.63 0.57 2.57 5.13 4.48 3.95 0.78 0.03 0.23 0.87 1.07 1.33 2.37 1.38 1.97 0.43 4.27 3.75 stencil opening edge position (for reference) top view 2.75 5.95 1.22 1.98 1.48 3.53 4.13 4.53 5.13 0.00 0.88 0.48 0.53 1.13 1.53 2.13 2.53 3.13 0.13 8.35 7.75 7.35 5.48 4.88 3.48 4.48 3.88 2.88 2.48 1.88 8.35 8.60 7.75 7.35 2.35 2.35 4.75 6.75 6.35 5.75 5.35 3.35 2.75 4.75 6.75 6.35 5.75 5.35 3.35 4.35 3.75 2.75 0.25 1.75 1.35 0.00 0.75 0.35 0.65 1.25 2.75 1.75 1.35 0.00 0.75 7.65 2.95 6.25 6.75 6.95 1.48 3.28 0.00 5.73 1.53 5.13 0.48 2.39 8.15 0.13 5.73 2.48 5.28 8.25 8.60 3.48 pcb land pattern (for reference) top view

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